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On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.

, , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 819-828. Springer, (2004)

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On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication., , , , and . ReCoSoC, page 185-191. Univ. Montpellier II, (2007)The XPP Architecture and Its Co-simulation Within the Simulink Environment., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 761-770. Springer, (2004)Power Consumption in Point-to-Point Interconnect Architectures., , , and . SBCCI, page 155-162. IEEE Computer Society, (2002)Functional modeling techniques for a wireless LAN OFDM transceiver., , , and . ISCAS (4), page 3970-3973. IEEE, (2005)Low-Power Coding for Networks-on-Chip with Virtual Channels., , , and . J. Low Power Electron., 5 (1): 77-84 (2009)Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks., , , , , and . ReCoSoC, page 151-156. Univ. Montpellier II, (2005)HW/SW design and realization of a size-reconfigurable DCT accelerator., , , and . ICECS, page 1-4. IEEE, (2005)An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs., , , and . DATE, page 698-703. ACM, (2008)Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System., , , and . IEEE International Workshop on Rapid System Prototyping, page 138-. IEEE Computer Society, (2002)Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance., , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 169-180. Springer, (2006)