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Disambiguation of "Matos, Debora"

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Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark.

, , , , , and . ICECS, page 408-411. IEEE, (2016)

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Mijo Matosevic

Luis Nuno Matos Pimentão

Narciso Matos

Debora Mascheroni

Debora Zeh

 

Other publications of authors with the same name

Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip., , , , , , , , and . ICECS, page 125-128. IEEE, (2013)Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability., , , , , and . ARC, volume 7806 of Lecture Notes in Computer Science, page 179-184. Springer, (2013)A power-efficient hierarchical network-on-chip topology for stacked 3D ICs., , , and . VLSI-SoC, page 308-313. IEEE, (2013)Adaptive multiple switching strategy toward an ideal NoC., , , , and . ISCAS, page 1014-1017. IEEE, (2014)Performance evaluation of hierarchical NoC topologies for stacked 3D ICs., , , , and . ISCAS, page 1961-1964. IEEE, (2015)NoC Power Optimization Using a Reconfigurable Router., , , , , and . ISVLSI, page 235-240. IEEE Computer Society, (2009)Network interface to synchronize multiple packets on NoC-based Systems-on-Chip., , , and . VLSI-SoC, page 31-36. IEEE, (2010)Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs., , and . ISCAS, page 4177-4180. IEEE, (2010)Floorplan-aware hierarchical NoC topology with GALS interfaces., , , , , , and . ISCAS, page 652-655. IEEE, (2012)Architectural exploration of Last-Level Caches targeting homogeneous multicore systems., , , , and . SBCCI, page 1-6. IEEE, (2016)