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Disambiguation of "Han, Yinhe"

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Architecting Effectual Computation for Machine Learning Accelerators.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2654-2667 (2020)

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Johannes Han

Bing Han

Luyang Han

Mei Han

Muxin Han

 

Other publications of authors with the same name

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator., , , , , and . IEEE Comput. Archit. Lett., 18 (1): 6-9 (2019)LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks., , , , and . IEEE Comput. Archit. Lett., 21 (1): 29-32 (2022)Integrating Two Logics Into One Crossbar Array for Logic Gate Design., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2987-2991 (2021)ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation., , and . IEEE Trans. Computers, 60 (9): 1219-1232 (2011)A New Multiple-Round Dimension-Order Routing for Networks-on-Chip., , , and . IEICE Trans. Inf. Syst., 94-D (4): 809-821 (2011)EcoUp: Towards Economical Datacenter Upgrading., , , and . IEEE Trans. Parallel Distributed Syst., 27 (7): 1968-1981 (2016)M-IVC: Applying multiple input vectors to co-optimize aging and leakage., and . Microelectron. J., 43 (11): 838-847 (2012)RBDCore: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines., , and . CoRR, (2023)RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3053-3064 (2015)Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (5): 531-540 (2007)