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Exact Path Delay Fault Coverage Calculation of Partitioned Circuits.

, , and . IEEE Trans. Computers, 58 (6): 858-864 (2009)

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On-Line Pruning of ZBDD for Path Delay Fault Coverage Calculation., , and . IEICE Trans. Inf. Syst., 88-D (7): 1381-1388 (2005)A nonenumerative algorithm to find the k longest (shortest) paths in a DAG. CoRR, (2013)Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA., , , , and . FPL, page 368-373. IEEE Computer Society, (2010)Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times., , and . ERSA, page 182-190. CSREA Press, (2007)Acyclic circuit partitioning for path delay fault emulation., and . AICCSA, page 22. IEEE Computer Society, (2005)Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays., and . FPL, volume 3203 of Lecture Notes in Computer Science, page 289-300. Springer, (2004)Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware., and . J. Electron. Test., 23 (5): 405-420 (2007)Exact Path Delay Fault Coverage Calculation of Partitioned Circuits., , and . IEEE Trans. Computers, 58 (6): 858-864 (2009)Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA., , , and . CICC, page 147-150. IEEE, (2000)Massively Parallel/Reconfigurable Emulation Model for the D-algorithm., , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 1172-1176. Springer, (2002)