( en | de | ru )

 

Disambiguation of "Sisto, Giuliano"

Author of the publication

copydeleteadd this publication to your clipboard
Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs.

, , , , , , , , , , and . 3DIC, page 1-4. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Giuliano Ramadori

Naoum Sistovaris

Giuliano Gregori

Giuliano Borrelli

Giovanna Giuliano

 

Other publications of authors with the same name

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)., , , , , , and . SLIP, page 17-23. IEEE, (2021)Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper., , , , , , and . SLIP, page 3:1-3:5. ACM, (2022)Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (10): 1497-1506 (2022)Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs., , , , , , , , , and 1 other author(s). 3DIC, page 1-4. IEEE, (2023)Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 429-430. IEEE, (2022)Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route., , , , , , and . 3DIC, page 1-4. IEEE, (2019)