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FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp., , , and . ASICON, page 1-4. IEEE, (2013)An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles., and . ISCAS (6), page 258-261. IEEE, (1999)Propagation Delay in RLC Interconnection Networks., and . ISCAS, page 2125-2128. IEEE, (1993)Optimization of VLSI Allocation., and . ISCAS, page 1065-1068. IEEE, (1995)RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect., , , and . ISCAS, page 2710-2713. IEEE, (2007)Frequency driven repeater insertion for deep submicron., , , and . ISCAS (5), page 181-184. IEEE, (2004)Efficient SVM-based hotspot detection using spectral clustering., , , and . ISCAS, page 1-4. IEEE, (2017)Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design., , , , and . ICML, volume 80 of Proceedings of Machine Learning Research, page 3312-3320. PMLR, (2018)Optimization and Quality Estimation of Circuit Design via Random Region Covering Method., , , and . ACM Trans. Design Autom. Electr. Syst., 23 (1): 1:1-1:25 (2017)LVS verification across multiple power domains for a quad-core microprocessor., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 11 (2): 490-500 (2006)