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Test Configurations for Diagnosing Faulty Links in NoC Switches.

, , and . ETS, page 29-34. IEEE Computer Society, (2007)

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Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)From RTL Liveness Assertions to Cost-Effective Hardware Checkers., , , and . DCIS, page 1-6. IEEE, (2018)Hybrid Protection of Digital FIR Filters., , , , , , and . CoRR, (2023)RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems., , , , , , , , , and 8 other author(s). CoRR, (2019)Parallel X-fault simulation with critical path tracing technique., , , and . DATE, page 879-884. IEEE Computer Society, (2010)Hierarchical Identification of Untestable Faults in Sequential Circuits., , , and . DSD, page 668-671. IEEE Computer Society, (2007)Fault Diagnosis in Integrated Circuits with BIST., , , , and . DSD, page 604-610. IEEE Computer Society, (2007)An Automatic Approach to Evaluate Assertions' Quality Based on Data-Mining Metrics., , , and . ITC-Asia, page 61-66. IEEE, (2018)Mutation analysis for SystemC designs at TLM., , , , , , , and . LATW, page 1-6. IEEE, (2011)High-Level Decision Diagrams based coverage metrics for verification and test., , , , and . LATW, page 1-6. IEEE, (2009)