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Disambiguation of "Wu, David M."

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An optimized delay testing technique for LSSD-based VLSI logic circuits.

. VTS, page 239-248. IEEE Computer Society, (1991)

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David M Eche

David M Eche

David M Stec

David M Allen

David A M Goslings

 

Other publications of authors with the same name

Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits., and . DAC, page 291-295. ACM, (1991)Cold Delay Defect Screening., , , and . VTS, page 183-188. IEEE Computer Society, (2000)DFT is all I can afford, who cares about Design for Yield or Design for Reliability!. ITC, page 1141-1142. IEEE Computer Society, (1999)Multiple redundancy removal during test generation and synthesis., and . VTS, page 274-279. IEEE Computer Society, (1992)Testing the impact of process defects on ECL power-delay performance., , and . VTS, page 233-238. IEEE Computer Society, (1991)Statistical AC Test Coverage., , and . ITC, page 538-541. IEEE Computer Society, (1986)H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing., , , , , , , , and . ITC, page 1229-1238. IEEE Computer Society, (2003)An optimized delay testing technique for LSSD-based VLSI logic circuits.. VTS, page 239-248. IEEE Computer Society, (1991)An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor., , , , , and . ITC, page 38-47. IEEE Computer Society, (2004)A Low Cost, High Quality Embedded Array DFT Technique for High Performance Processors., , , , and . DELTA, page 57-63. IEEE Computer Society, (2006)