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Hardware design methodology using lightweight dataflow and its integration with low power techniques.

, , , , , , , , , и . J. Syst. Archit., (2017)

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Tiziana Margaria

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Robert Joseph Fanning

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Run-time performance monitoring of hardware accelerators: POSTER., и . CF, стр. 289-291. ACM, (2019)Hardware design methodology using lightweight dataflow and its integration with low power techniques., , , , , , , , , и . J. Syst. Archit., (2017)Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems., и . ReConFig, стр. 1-4. IEEE, (2016)Verification of Neural Networks: Challenges and Perspectives in the AIDOaRt Project (Short Paper)., , , , , и . IPS/RiCeRcA/SPIRIT@AI*IA, том 3345 из CEUR Workshop Proceedings, CEUR-WS.org, (2022)NeuPow: artificial neural networks for power and behavioral modeling of arithmetic components in 45nm ASICs technology., , , , , , и . CF, стр. 183-189. ACM, (2019)Power and clock gating modelling in coarse grained reconfigurable systems., , , , и . Conf. Computing Frontiers, стр. 384-391. ACM, (2016)Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI., , , , , , , , и . CoRR, (2021)Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures., , , , и . J. Electr. Comput. Eng., (2016)Layering the monitoring action for improved flexibility and overhead control: work-in-progress., , , и . CoRR, (2021)Power modelling for saving strategies in coarse grained reconfigurable systems., , , , и . ReConFig, стр. 1-4. IEEE, (2015)