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Chainsaw: Von-neumann accelerators to leverage fused instruction chains.

, , , and . MICRO, page 49:1-49:14. IEEE Computer Society, (2016)

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Systematic evaluation of workload clustering for extremely energy-efficient architectures., , , and . SIGARCH Comput. Archit. News, 41 (2): 22-29 (2013)μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators., , , , , , and . MICRO, page 940-953. ACM, (2019)On the applicability of simple cache models for modern processors., , and . ICGHPC, page 1-7. IEEE, (2016)Poster: An Exascale Workload Study., , , , , , , , and . SC Companion, page 1465. IEEE Computer Society, (2012)Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators., , and . PACT, page 68-81. IEEE, (2019)Reducing Exit Stub Memory Consumption in Code Caches., , and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 87-101. Springer, (2007)The interaction of last-level-cache mechanisms on modern processors., , and . MEMSYS, page 249-250. ACM, (2017)Exascale workload characterization and architecture implications., , , , , , , , and . ISPASS, page 120-121. IEEE Computer Society, (2013)Easy and expressive LLC contention model., , and . HPCS, page 372-379. IEEE, (2016)Balancing memory and performance through selective flushing of software code caches., , and . CASES, page 1-10. ACM, (2010)