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A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF.

, , and . HOST, page 157. IEEE Computer Society, (2017)

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Secure Design Flow of FPGA Based RISC-V Implementation., , , , , and . IVSW, page 37-42. IEEE, (2019)Dynamic Key Updates for LUT Locked Design., , , , , and . HOST, page 105-108. IEEE, (2022)An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays., , , , , , and . Cryptogr., 2 (3): 15 (2018)Leveraging Distributions in Physical Unclonable Functions., , , and . Cryptogr., 1 (3): 17 (2017)Multilayer Camouflaged Secure Boot for SoCs., , , , , , and . MTV, page 56-61. IEEE, (2019)ASIC implementation of a hardware-embedded physical unclonable function., , , and . IET Comput. Digit. Tech., 8 (6): 288-299 (2014)A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic., , , , and . J. Hardw. Syst. Secur., 5 (3): 260-268 (2021)A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture., , and . MWSCAS, page 718-721. IEEE, (2020)A Delay-Based Machine Learning Model for DMA Attack Mitigation., , , and . Cryptogr., 5 (3): 18 (2021)GDS-II Trojan detection using multiple supply pad VDD and GND IDDQs in ASIC functional units., , and . HOST, page 144-150. IEEE Computer Society, (2015)