( en | de | ru )

 

Disambiguation of "Kundu, Somnath"

Author of the publication

copydeleteadd this publication to your clipboard
22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking.

, , , , , , , and . ISSCC, page 392-394. IEEE, (2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Somnath Ghosh

Arijit Kundu

Somnath Bhattacharyya

Somnath Ghosh

Shankhamala Kundu

 

Other publications of authors with the same name

A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection., , and . IEEE J. Solid State Circuits, 52 (3): 799-811 (2017)A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer., , , , and . IEEE J. Solid State Circuits, 54 (1): 109-120 (2019)A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer., , , and . IEEE J. Solid State Circuits, 53 (4): 1203-1213 (2018)Evacuating from ℓp Unit Disks in the Wireless Model - (Extended Abstract)., , , and . ALGOSENSORS, volume 12961 of Lecture Notes in Computer Science, page 76-93. Springer, (2021)A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW., , , , , , , , , and . VLSI Technology and Circuits, page 170-171. IEEE, (2022)Makespan Trade-Offs for Visiting Triangle Edges - (Extended Abstract)., , and . IWOCA, volume 12757 of Lecture Notes in Computer Science, page 340-355. Springer, (2021)A 44 GHz Quadrature Traveling Wave Oscillator., and . VLSI Design, page 179-184. IEEE Computer Society, (2013)A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology., , , , , , , , , and 6 other author(s). ISSCC, page 174-176. IEEE, (2019)A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 58 (12): 3364-3379 (December 2023)A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW., , , , , , , , , and . IEEE J. Solid State Circuits, 58 (4): 972-982 (2023)