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On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation.

, and . ISMVL, page 221-228. IEEE Computer Society, (1992)

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Topological Properties of Hierarchical Interconnection Networks: A Review and Comparison., and . J. Electr. Comput. Eng., (2011)Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (12): 2683-2695 (2007)Design and analysis of reliablle and fault-tolerant computer systems.. Imperial College Press, (2007)A Comparative Study of Programmable Realization Techniques of Multi-Valued Multi-Threshold Functions., , , and . ISMVL, page 372-381. IEEE Computer Society, (1991)Step-Wise Synthesis of CCD MVL Functions., , and . ISMVL, page 300-307. IEEE Computer Society, (1990)Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm., , and . ISMVL, page 216-221. IEEE Computer Society, (1995)Decomposition-Based Synthesis of Multiple-Valued Functions for Threshold Logic Network Realization., and . ISMVL, page 58-64. IEEE Computer Society, (1994)A New Improved Cost-Table-Based Technique for Synthesis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits., and . ISMVL, page 15-20. IEEE Computer Society, (2001)Reducing the Cost of Test Pattern Generation by Information Reusing., , and . ICCD, page 310-313. IEEE Computer Society, (1993)A High-Performance Hardware-Efficient Memory Allocation Technique and Design., , and . ICCD, page 274-276. IEEE Computer Society, (1999)