( en | de | ru )

 

Disambiguation of "Stouraitis, Thanos"

Author of the publication

copydeleteadd this publication to your clipboard
An efficient probabilistic method for logic circuits using real delay gate model.

, , , , and . ISCAS (1), page 286-289. IEEE, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Thanos Lipowatz

Melissa Thanos

Ioannis Thanos

Thanos Rigas

Solon Thanos

 

Other publications of authors with the same name

Outage probability of single carrier NOMA systems under I/Q imbalance., , , , , , and . WCNC, page 1-6. IEEE, (2018)Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs., , , , , and . Journal of Circuits, Systems, and Computers, 25 (4): 1650032:1-1650032:26 (2016)Novel high-radix residue number system multipliers and adders., and . ISCAS (1), page 451-454. IEEE, (1999)Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP., , and . ISCAS, IEEE, (2006)Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors., and . ISCAS, page 79-82. IEEE, (1994)An RNS barrett modular multiplication architecture., and . ISCAS, page 2229-2232. IEEE, (2014)A complex DSP processor using polynomial encoding., , and . ICASSP, page 1310-1313. IEEE, (1989)A hybrid floating-point/logarithmic number system digital signal processor.. ICASSP, page 1079-1082. IEEE, (1989)Approximate Logarithmic Multiplier For Convolutional Neural Network Inference With Computational Reuse., , , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Systematic design of full adder-based architectures for convolution., , , , and . ICASSP (1), page 389-392. IEEE Computer Society, (1993)