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Semantic information based speculative parallel execution

, and . Pespma 2010 - Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture, Saint Malo, France, ()

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A compiler algorithm that reduces read latency in ownership-based cache coherence protocols., and . PACT, page 69-78. IFIP Working Group on Algol / ACM, (1995)Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination., and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 52-66. Springer, (2006)High-Performance Embedded Architecture and Compilation Roadmap., , , , , , , , , and 1 other author(s). Trans. High Perform. Embed. Archit. Compil., (2007)Starvation-free commit arbitration policies for transactional memory systems., and . SIGARCH Comput. Archit. News, 35 (1): 39-46 (2007)Improving power efficiency of D-NUCA caches., , , , and . SIGARCH Comput. Archit. News, 35 (4): 53-58 (2007)A Survey of Cache Coherence Schemes for Multiprocessors.. Computer, 23 (6): 12-24 (1990)DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors., , , and . IPDPS, page 578-589. IEEE, (2020)The Velox Transactional Memory Stack., , , , , , , , , and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems., , and . IPDPS, page 303-313. IEEE, (2019)Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems., , , and . CoRR, (2019)