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Scalable Hardware Memory Disambiguation for High-ILP Processors., , , , and . IEEE Micro, 24 (6): 118-127 (2004)Static energy reduction techniques for microprocessor caches., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 303-313 (2003)A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips., , , and . IEEE Micro, 32 (3): 17-25 (2012)Structurally Sparsified Backward Propagation for Faster Long Short-Term Memory Training., , , , , and . CoRR, (2018)A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors., , , , , , and . ACM Trans. Comput. Syst., 30 (2): 8:1-8:38 (2012)Estimating Silent Data Corruption Rates Using a Two-Level Model., , , , , , , , , and . CoRR, (2020)The impact of delay on the design of branch predictors., , and . MICRO, page 67-76. ACM/IEEE Computer Society, (2000)Universal Mechanisms for Data-Parallel Architectures., , , and . MICRO, page 303-314. IEEE Computer Society, (2003)Simba: scaling deep-learning inference with chiplet-based architecture., , , , , , , , , and 7 other author(s). Commun. ACM, 64 (6): 107-116 (2021)Community-based Matrix Reordering for Sparse Linear Algebra Optimization., , , and . ISPASS, page 214-223. IEEE, (2023)