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Disambiguation of "Joseph, Jan Moritz"

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Adaptive allocation of default router paths in Network-on-Chips for latency reduction.

, , and . HPCS, page 140-147. IEEE, (2016)

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Jan Joseph

Jan Moritz Voswinckel

Jan Robert Moritz

Jan Moritz Middeke

Jan-Moritz Doehn

 

Other publications of authors with the same name

Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , and . CoRR, (2020)Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware., , , , , , and . DAC, page 1-6. IEEE, (2023)Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies., , and . NANOCOM, page 17:1-17:7. ACM, (2021)Optimising Operator Sets for Analytical Database Processing on FPGAs., , , , , and . ARC, volume 12083 of Lecture Notes in Computer Science, page 30-44. Springer, (2020)A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars., , , , , and . AICAS, page 537-538. IEEE, (2024)parti-gem5: gem5's Timing Mode Parallelised., , , , and . SAMOS, volume 14385 of Lecture Notes in Computer Science, page 177-192. Springer, (2023)Design method for asymmetric 3D interconnect architectures with high level models., , , , , and . ReCoSoC, page 1-8. IEEE, (2017)Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs., , , and . NORCAS, page 1-4. IEEE, (2015)Hardware-accelerated pose estimation for embedded systems using Vivado HLS., , , , and . ReConFig, page 1-7. IEEE, (2016)Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS., , , , , and . ReConFig, page 1-8. IEEE, (2017)