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Disambiguation of "Ho, Cheng-Ru"

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29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur.

, , , and . ISSCC, page 410-412. IEEE, (2021)

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Patience Ching-Ru Ho

Patience Ching-Ru Ho

Patience Ching-Ru Ho

Patience Ching-Ru Ho

Cheng-Yung Cheng

 

Other publications of authors with the same name

A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers., , , , , , , , , and 16 other author(s). OFC, page 1-3. IEEE, (2023)A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling., and . ISSCC, page 254-256. IEEE, (2018)A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter., , and . IEEE J. Solid State Circuits, 52 (9): 2335-2349 (2017)8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET., , , , , , , , , and 18 other author(s). ISSCC, page 138-140. IEEE, (2021)10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS., and . ISSCC, page 190-191. IEEE, (2016)A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS., , and . CICC, page 1-4. IEEE, (2015)A Fractional-N Digital MDLL With Background Two-Point DTC Calibration., , , and . IEEE J. Solid State Circuits, 57 (1): 80-89 (2022)Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS., and . ESSCIRC, page 213-216. IEEE, (2016)A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme., and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (8): 1111-1122 (2016)29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur., , , and . ISSCC, page 410-412. IEEE, (2021)