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A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS.

, , , , , , , , and . CICC, page 1-4. IEEE, (2014)

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Maximizing Science in the Era of LSST: A Community-Based Study of Needed US Capabilities, , , , , , , , , and 41 other author(s). (Oct 5, 2016)A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2014)Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology., , , , , , , , and . CICC, page 1-3. IEEE, (2015)A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem., , , , , , , , , and 20 other author(s). ISSCC, page 54-56. IEEE, (2021)DI-MMAP - a scalable memory-map runtime for out-of-core data-intensive applications., , , , and . Clust. Comput., 18 (1): 15-28 (2015)R2-D2: Roman and Rubin -- From Data to Discovery, , , , , , , , , and 21 other author(s). (2022)cite arxiv:2202.12311Comment: 29 pages, 12 figures, Table of Implementation Recommendations, Appendix of Community Science Pitches, AURA-commissioned whitepaper submitted to the Director of STScI (Ken Sembach) and the Director of NOIRLab (Pat McCarthy).DI-MMAP: A High Performance Memory-Map Runtime for Data-Intensive Applications., , , and . SC Companion, page 731-735. IEEE Computer Society, (2012)