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Towards a Digital Twin Architecture with Formal Analysis Capabilities for Learning-Enabled Autonomous Systems.

, , , , , , , and . MESAS, volume 13866 of Lecture Notes in Computer Science, page 163-181. Springer, (2022)

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A novel approach for assertion based verification of DDR memory protocols., , , and . FDL, page 1-4. IEEE, (2013)Formal Verification of Digital Circuits.. IWSOC, page 15. IEEE Computer Society, (2004)Formal Based Methodology for Inferring Memory Mapped Registers., , and . MTV, page 15-18. IEEE Computer Society, (2016)TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip., , , and . MTV, page 1-4. IEEE Computer Society, (2011)Automatic test pattern generation for virtual hardware model using constrained symbolic execution., , , and . IDT, page 149-150. IEEE, (2015)SoC verification platforms using HW emulation and co-modeling Testbench technologies., and . IDT, page 14-19. IEEE, (2015)Towards Automating Hardware/Software Co-Design., , , , and . IWSOC, page 189-192. IEEE Computer Society, (2004)M-CHECK: a multiple engine combinational equivalence checker., , and . ISCAS, page 613-616. IEEE, (2000)A novel approach for system level synthesis of multi-core system architectures from TPG models., , , , and . AICCSA, page 268-275. IEEE Computer Society, (2011)Anomaly Detection System for Altered Signal Values within the Intra-Vehicle Network., , and . DTIS, page 1-6. IEEE, (2020)