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Analyzing data reuse for cache reconfiguration., , , and . ACM Trans. Embed. Comput. Syst., 4 (4): 851-876 (2005)Exploring Wakeup-Free Instruction Scheduling., , and . HPCA, page 232-243. IEEE Computer Society, (2004)BTB Access Filtering: A Low Energy and High Performance Design., , and . ISVLSI, page 81-86. IEEE Computer Society, (2008)TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array., , and . ISVLSI, page 310-315. IEEE Computer Society, (2010)Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors., , , and . DFT, page 92-97. IEEE Computer Society, (2012)Asymmetrically banked value-aware register files for low-energy and high-performance., , , and . Microprocess. Microsystems, 32 (3): 171-182 (2008)Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays., , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (4): 643-654 (2012)Scheduling Reusable Instructions for Power Reduction., , , , and . DATE, page 148-155. IEEE Computer Society, (2004)Asymmetrically Banked Value-Aware Register Files., , , and . ISVLSI, page 363-368. IEEE Computer Society, (2007)Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors., , and . ERSA, page 61-70. CSREA Press, (2007)