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On-chip process variation-tracking through an all-digital monitoring architecture.

, , , , и . IET Circuits Devices Syst., 6 (5): 366-373 (2012)

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Massimo Viola

Massimo Malagó

Massimo Moser

Massimo Tallarida

Massimo Busin

 

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Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , и . DAC, стр. 467-470. ACM Press, (1996)Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control., , и . DAC, стр. 22-27. ACM Press, (1997)Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms., , , , и . DAC, стр. 247-252. ACM Press, (1999)Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip., , и . ISCAS (2), стр. 361-364. IEEE, (2004)A hierarchical multi-level test generation system., и . Great Lakes Symposium on VLSI, стр. 54-59. IEEE, (1991)Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting., , , , , и . IEEE Trans. Computers, 48 (8): 769-779 (1999)Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs., , , и . PATMOS, том 3728 из Lecture Notes in Computer Science, стр. 466-476. Springer, (2005)Energy-Efficient Shared Memory Architectures for Multi-Processor Systems-On-Chip., , и . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)Post-placement temperature reduction techniques., , , , и . DATE, стр. 634-637. IEEE Computer Society, (2010)Workload-driven frequency-aware battery sizing., , и . ISLPED, стр. 1-6. IEEE, (2017)