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Disambiguation of "Sasan, Avesta"

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Threats on Logic Locking: A Decade Later.

, , , and . CoRR, (2019)

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Ahmad Sasani Nejad

Sasan Maleki

Sasan Partovi

Sasan Cyrusian

Sasan Shaheen

 

Other publications of authors with the same name

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring., , , , and . ISQED, page 498-505. IEEE, (2012)Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization., , , , , , , and . IEEE Access, (2023)Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (6): 56:1-56:29 (2022)Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance., , and . Near Threshold Computing, Springer, (2016)ICNN: The Iterative Convolutional Neural Network., , and . ACM Trans. Embed. Comput. Syst., 18 (6): 119:1-119:27 (2020)CPM: A general feature dependency pattern mining framework for contrast multivariate time series., , , , and . Pattern Recognit., (2021)A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)., , , and . CASES, page 251-260. ACM, (2009)Repttack: Exploiting Cloud Schedulers to Guide Co-Location Attacks., , , , , , , and . NDSS, The Internet Society, (2022)HybriDG: Hybrid Dynamic Time Warping and Gaussian Distribution Model for Detecting Emerging Zero-Day Microarchitectural Side-Channel Attacks., , , , and . ICMLA, page 604-611. IEEE, (2020)Learning Assisted Side Channel Delay Test for Detection of Recycled ICs., , , , and . ASP-DAC, page 455-462. ACM, (2021)