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Disambiguation of "Richards, Brian C."

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ASIC Design and Verification in an FPGA Environment.

, , , , , and . CICC, page 737-740. IEEE, (2007)

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Brian C Dennert

Brian C Castle

Rolf-Walter Briant

Benoît Briand

Gisela Richards

 

Other publications of authors with the same name

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 54 (10): 2786-2801 (2019)An integrated CAD system for algorithm-specific IC design., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (4): 447-463 (1991)Implementation of BEE: a real-time large-scale hardware emulation engine., , , and . FPGA, page 91-99. ACM, (2003)HDBinaryCore: A 28nm 2048-bit Hyper-Dimensional biosignal classifier achieving 25 nJ/prediction for EMG hand-gesture recognition., , , , , and . ESSCIRC, page 229-232. IEEE, (2023)A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET., , , , , , , , , and . A-SSCC, page 305-308. IEEE, (2017)Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 148-. IEEE Computer Society, (2003)Design of Wireless Portable Systems., , , , , , , , , and 3 other author(s). COMPCON, page 169-176. IEEE Computer Society, (1995)A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band., , and . IEEE J. Solid State Circuits, 46 (11): 2524-2534 (2011)Describing MIMO designs for rapid prototyping in the BEE environment., , , , , and . EUSIPCO, page 693-696. IEEE, (2004)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)