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O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (9): 3056-3069 (2020)

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Workload Imbalance in HPC Applications: Effect on Performance of In-Network Processing., , , , and . HPEC, page 1-8. IEEE, (2021)A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs., , , , , , , , , and . HPEC, page 1-8. IEEE, (2021)A Reconfigurable Compute-in-the-Network FPGA Assistant for High-Level Collective Support with Distributed Matrix Multiply Case Study., , , , , , and . FPT, page 159-164. IEEE, (2020)A Framework for Neural Network Inference on FPGA-Centric SmartNICs., , , , , , , , and . FPL, page 1-8. IEEE, (2022)FLASH: FPGA-Accelerated Smart Switches with GCN Case Study., , , , , , , , , and 2 other author(s). ICS, page 450-462. ACM, (2023)FP-AMG: FPGA-Based Acceleration Framework for Algebraic Multigrid Solvers., , , , and . FCCM, page 148-156. IEEE, (2020)AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing., , , , , , , , , and 1 other author(s). MICRO, page 922-936. IEEE, (2020)A Survey of Potential MPI Complex Collectives: Large-Scale Mining and Analysis of HPC Applications., , , , and . CoRR, (2023)O⁴-DNN: A Hybrid DSP-LUT-Based Processing Unit With Operation Packing and Out-of-Order Execution for Efficient Realization of Convolutional Neural Networks on FPGA Devices., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (9): 3056-3069 (2020)COPA Use Case: Distributed Secure Joint Computation., , , , , , and . FCCM, page 1-2. IEEE, (2022)