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Disambiguation of "Kumar, Chaudhry Indra"

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An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN.

, , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2311-2315 (2022)

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Umer Chaudhry

Waheed Chaudhry

Arsianiwaty Indradjaja

Selvaratnam Indrakumar

Gunawan Indrayanto

 

Other publications of authors with the same name

A novel energy-efficient self-correcting methodology employing INWE., , , and . SMACD, page 1-4. IEEE, (2016)Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications., and . Integr., (2022)Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications., , and . Integr., (March 2024)An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance., , and . ISVLSI, page 49-53. IEEE Computer Society, (2011)High performance energy efficient radiation hardened latch for low voltage applications., and . Integr., (2019)A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2170-2179 (2019)An energy-efficient variation aware self-correcting latch., , , and . Microelectron. J., (2019)Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability., and . PRIME, page 101-104. IEEE, (2018)An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (4): 2311-2315 (2022)An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design.. J. Circuits Syst. Comput., 31 (7): 2250125:1-2250125:16 (2022)