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An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer.

, , , , and . IEEE J. Solid State Circuits, 58 (4): 929-938 (2023)

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Synthesizable ADPLL Generator: From Specification to GDS., and . SMACD, page 1-4. IEEE, (2023)An Open-source Framework for Autonomous SoC Design with Analog Block Generation., , , , , , , , , and 3 other author(s). VLSI-SOC, page 141-146. IEEE, (2020)Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation., , , , , , , , , and 5 other author(s). VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 65-85. Springer, (2020)PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter., , and . IEEE J. Solid State Circuits, 58 (5): 1271-1284 (May 2023)An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer., , , , and . VLSI Technology and Circuits, page 54-55. IEEE, (2022)An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer., , , , and . IEEE J. Solid State Circuits, 58 (4): 929-938 (2023)A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates., , , , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 16 (3): 395-408 (2022)