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Disambiguation of "Flynn, Michael P."

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A 16-channel noise-shaping machine learning analog-digital interface.

, , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Robynne Flynn-Diez

Choi-Yeung-Chang Flynn

Sharon Flynn

Linda Jessica Flynn

Michael P Maier

 

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EP2: You're hired! The top 25 interview questions for circuit designers., and . ISSCC, page 516. IEEE, (2013)A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders., , , , , and . VLSIC, page 70-71. IEEE, (2012)Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression., , , , , and . VLSIC, page 108-. IEEE, (2015)A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS., and . ESSCIRC, page 1-4. IEEE, (2019)A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (12): 2846-2857 (2012)A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers., and . IEEE J. Solid State Circuits, 50 (10): 2331-2341 (2015)A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 52 (10): 2735-2745 (2017)A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC., , , and . IEEE J. Solid State Circuits, 45 (9): 1935-1945 (2010)New Associate Editor.. IEEE J. Solid State Circuits, 48 (9): 1999 (2013)A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS., , , and . IEEE J. Solid State Circuits, 53 (5): 1302-1312 (2018)