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VLSI Performance of Multistage Interconnection Network Using 4*4 Switches., and . ICDCS, page 606-613. IEEE Computer Society, (1982)Finite Buffer Analysis of Multistage Interconnection Networks., and . IEEE Trans. Computers, 43 (2): 243-247 (1994)Performance Evaluation of a Dataflow Architecture., and . IEEE Trans. Computers, 39 (5): 615-627 (1990)Design and Performance of Generalized Interconnection Networks., and . IEEE Trans. Computers, 32 (12): 1081-1090 (1983)Bandwidth Availability of Multiple-Bus Multiprocessors., and . IEEE Trans. Computers, 34 (10): 918-926 (1985)Fair Scheduling in Internet Routers., and . IEEE Trans. Computers, 51 (6): 686-701 (2002)Evaluating Virtual Channels for Cache-Coherent Shared-Memory Multiprocessors., and . International Conference on Supercomputing, page 253-260. ACM, (1996)A new IP lookup cache for high performance IP routers., , and . DAC, page 338-343. ACM, (2010)Extending Multistage Interconnection Networks for Multitasking., and . ICPP (1), page 151-158. CRC Press, (1992)Reliability Simulation of Multiprocessor Systems., and . ICPP, page 591-598. IEEE Computer Society Press, (1985)