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A unioned graph neural network based hardware Trojan node detection.

W. Pan, M. Dong, C. Wen, H. Liu, S. Zhang, B. Shi, Z. Di, Z. Qiu, Y. Gao, and L. Zheng. IEICE Electron. Express, 20 (13): 20230204 (2023)

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Weiqing Pan

Yaling Pan

Pan Li

Alexey Pan

Xiaoqing Pan

Other publications of authors with the same name

DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory.C. Duan, J. Yang, X. He, Y. Qi, Y. Wang, Y. Wang, Z. He, B. Yan, X. Wang, X. Jia and 2 other author(s). CoRR, (2023)Improved analytical model for performance evaluation of crosspoint-queued switch under uniform traffic.Y. Gao, W. Pan, and L. Zheng. IET Networks, 6 (4): 81-86 (2017)Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches.L. Zheng, W. Pan, Y. Li, and Y. Gao. Int. J. Commun. Syst., (2020)The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow.Z. Qiu, W. Wang, S. Sun, W. Pan, L. Zheng, Y. Gao, and Z. Zhang. CITS, page 1-5. IEEE, (2018)Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric.L. Zheng, W. Pan, Y. Gao, H. Liu, and J. Jiang. Comput. Networks, (2021)Access mechanism for period flows of non-deterministic end systems for time-sensitive networks.Z. Zhao, L. Gao, W. Pan, Z. Qiu, X. Guo, Y. Gao, and L. Zheng. Comput. Networks, (July 2023)Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.J. Shi, X. Zhang, P. Ma, W. Pan, P. Li, and Z. Tang. IEEE Trans. Circuits Syst. II Express Briefs, 68 (6): 2152-2156 (2021)Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers.L. Zheng, Z. Qiu, S. Sun, W. Pan, Y. Gao, and Z. Zhang. J. Commun. Networks, 20 (6): 578-592 (2018)Dual priority congestion aware shared-resource Network-on-Chip architecture.H. Shu, J. Shi, P. Ma, H. Gu, W. Pan, and L. Yang. IEICE Electron. Express, 13 (7): 20160142 (2016)Design of HIMAC Coprocessor for HINOC3.0.J. Huang, Z. Qiu, W. Pan, J. Li, Z. Gao, B. Han, Z. Xiong, and M. Dong. ICCCS, page 1047-1052. IEEE, (2021)

BibSonomy

Disambiguation of "Pan, Weitao"

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A unioned graph neural network based hardware Trojan node detection.

Please choose a person to relate this publication to

Weiqing Pan

Yaling Pan

Pan Li

Alexey Pan

Xiaoqing Pan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pan, Weitao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A unioned graph neural network based hardware Trojan node detection.

Please choose a person to relate this publication to

Weiqing Pan

Yaling Pan

Pan Li

Alexey Pan

Xiaoqing Pan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A unioned graph neural network based hardware Trojan node detection.