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TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research.

, , , , , , , , , and . WCET, volume 55 of OASICS, page 2:1-2:10. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2016)

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Performance of M3S for the SOR algorithm., , and . PARLE, volume 694 of Lecture Notes in Computer Science, page 676-679. Springer, (1993)Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets., , and . ARCS, volume 7767 of Lecture Notes in Computer Science, page 341-351. Springer, (2013)Une approche pour réduire la complexité du flot de contrôle dans les programmes C., , , and . Tech. Sci. Informatiques, 21 (7): 1009-1032 (2002)Hardware architecture specification and constraint-based WCET computation., , , and . SIES, page 259-268. IEEE, (2013)Towards Designing WCET-Predictable Processors., and . WCET, MDH-MRTC-116/2003-1-SE, page 87-90. Department of Computer Science and Engineering, Mälardalen University, Box 883, 721 23 Västerås, Sweden, (2003)WCET 2007 Abstracts Collection - 7th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis.. WCET, volume 6 of OASIcs, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2007)Validation of Processor Timing Models Using Cycle-Accurate Timing Simulators., , , and . WCET, volume 114 of OASIcs, page 2:1-2:12. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)Predictable bus arbitration schemes for heterogeneous time-critical workloads running on multicore processors., , and . ETFA, page 1-4. IEEE, (2011)Using the abstract interpretation technique for static pointer analysis., , , and . SIGARCH Comput. Archit. News, 27 (1): 47-50 (1999)An Overview of Approaches Towards the Timing Analysability of Parallel Architecture.. PPES, volume 18 of OASIcs, page 32-41. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Germany, (2011)