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Disambiguation of "Schuster, Stanley"

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A circuit level implementation of an adaptive issue queue for power-aware microprocessors.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 73-78. ACM, (2001)

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Dolores Stanley

Stanley Heinze

Stanley Baksi

Stanley Durrleman

Stanley Tang

 

Other publications of authors with the same name

Design and characteristics of n-channel insulated-gate field-effect transistors., , and . IBM J. Res. Dev., 44 (1): 70-83 (2000)A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)Fast Low Power eDRAM Hierarchical Differential Sense Amplifier., and . IEEE J. Solid State Circuits, 44 (2): 631-641 (2009)Early-Stage Definition of LPX: A Low Power Issue-Execute Processor., , , , , , , , , and 6 other author(s). PACS, volume 2325 of Lecture Notes in Computer Science, page 1-17. Springer, (2002)Tradeoffs in power-efficient issue queue design., , , , and . ISLPED, page 184-189. ACM, (2002)Logic-based eDRAM: Origins and rationale for use., and . IBM J. Res. Dev., 49 (1): 145-166 (2005)Dynamically Tuning Processor Resources with Adaptive Processing., , , , , , , , , and 4 other author(s). Computer, 36 (12): 49-58 (2003)A circuit level implementation of an adaptive issue queue for power-aware microprocessors., , , , , and . ACM Great Lakes Symposium on VLSI, page 73-78. ACM, (2001)Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz., and . IEEE J. Solid State Circuits, 38 (4): 622-630 (2003)