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OC-3072 packet classification using BDDs and pipelined SRAMs.

, and . Hot Interconnects, page 15-20. IEEE Computer Society, (2001)

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The hazard-free superscalar pipeline fast fourier transform algorithm and architecture., , and . VLSI-SoC, page 194-199. IEEE, (2007)Optimizing Designs Containing Black Boxes., , , and . DAC, page 113-116. ACM Press, (1997)Hybrid Techniques for Fast Functional Simulation., , and . DAC, page 664-667. ACM Press, (1998)The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-22. Springer, (2007)An Abstraction Algorithm for the Verification of Generalized C-Slow Designs., , , , and . CAV, volume 1855 of Lecture Notes in Computer Science, page 5-19. Springer, (2000)Verifying Continuous Time Markov Chains., , , and . CAV, volume 1102 of Lecture Notes in Computer Science, page 269-276. Springer, (1996)VIS: A System for Verification and Synthesis., , , , , , , , , and 6 other author(s). CAV, volume 1102 of Lecture Notes in Computer Science, page 428-432. Springer, (1996)Theory of safe replacements for sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (2): 249-265 (2001)SIVA: A System for Coverage-Directed State Space Search., , , , and . J. Electron. Test., 17 (1): 11-27 (2001)Simultaneous routing and buffer insertion with restrictions onbuffer locations., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 819-824 (2000)