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Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.

, and . DAC, page 330-333. ACM, (2003)

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Reconditioning: Automatic Power Optimization of QDI Circuits., , and . ASYNC, page 77-84. IEEE Computer Society, (2014)SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces., and . CPA, volume 68 of Concurrent Systems Engineering Series, page 287-302. IOS Press, (2011)High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog., and . CPA, volume 63 of Concurrent Systems Engineering Series, page 275-288. IOS Press, (2005)Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction., and . DAC, page 330-333. ACM, (2003)Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (2): 265-278 (2017)Logical equivalence checking of asynchronous circuits using commercial tools., , , and . DATE, page 1563-1566. ACM, (2015)Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines., and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 205-214. Springer, (2012)MILO: personal robot platform., , , and . IROS, page 4089-4094. IEEE, (2005)Notes On Pulse Signaling., , and . ASYNC, page 15-24. IEEE Computer Society, (2007)