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Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis.

, , , , and . DAC, page 1331-1334. IEEE, (2021)

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A high-performance low-power near-Vt RRAM-based FPGA., , and . FPT, page 207-214. IEEE, (2014)An Enhanced Design Methodology for Resonant Clock Trees., , , and . J. Low Power Electron., 9 (2): 198-206 (2013)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)Post-P&R Performance and Power Analysis for RRAM-Based FPGAs., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 639-650 (2018)A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories., , , , , , , and . VLSI-SoC, page 160-165. IEEE, (2019)Optimization opportunities in RRAM-based FPGA architectures., , and . LASCAS, page 1-4. IEEE, (2017)Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (5): 1173-1186 (2017)A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs., , and . ISPD, page 135-142. ACM, (2021)ALICE: an automatic design flow for eFPGA redaction., , , , , , , , and . DAC, page 781-786. ACM, (2022)A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells., , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (10): 2187-2197 (2015)