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Disambiguation of "Lee, Kuen-Jong"

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An integrated system for assigning signal flow directions to CMOS transistors.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (12): 1445-1458 (1995)

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Jong-Kwan Lee

Jong-Ha Lee

Jong Wan Lee

Jong-Soo Lee

Jong-Won Lee

 

Other publications of authors with the same name

An Error Rate Based Test Methodology to Support Error-Tolerance., , and . IEEE Trans. Reliability, 57 (1): 204-214 (2008)An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs)., , and . ISCAS, page 393-396. IEEE, (1995)Transformation of multiple fault models to a unified model for ATPG efficiency enhancement., and . ITC, page 1-10. IEEE, (2016)An on-chip self-test architecture with test patterns recorded in scan chains., , and . ITC, page 1-10. IEEE, (2016)SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits., , and . DAC, page 26-29. IEEE Computer Society Press, (1992)Using Unstable SRAM Bits for Physical Unclonable Function Applications on Off-The-Shelf SRAM., and . APCCAS, page 41-44. IEEE, (2019)A low-cost SOC debug platform based on on-chip test architectures., , and . SoCC, page 161-164. IEEE, (2009)An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment., and . J. Electron. Test., 18 (1): 43-53 (2002)Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (6): 1340-1345 (2020)An on-chip march pattern generator for testing embedded memory cores., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (5): 730-735 (2001)