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Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments.

. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (1): 97-105 (2017)

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Benjamin Schäfer

Christoph Benjamin Schäfer

Ruperto Antonio Ugas Carrión

Monika Borst-Carrión Eguiguren

Víctor Manuel Pérez Abreu Carrión

 

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Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., и . FPT, стр. 193-196. IEEE, (2016)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., и . ICCD, стр. 524-531. IEEE, (2019)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., и . ICCAD, стр. 1-8. ACM, (2019)Autonomous temperature control technique in VLSI circuits through logic replication., и . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies.. ACM Trans. Design Autom. Electr. Syst., 22 (4): 65:1-65:20 (2017)Toward Self-Tunable Approximate Computing., и . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 778-789 (2019)Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis., , и . IOLTS, стр. 232-235. IEEE, (2018)Fixed Point Data Type Modeling for High Level Synthesis., , , , и . IEICE Trans. Electron., 93-C (3): 361-368 (2010)Precision tunable RTL macro-modelling cycle-accurate power estimation., и . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis., и . IEEE Embed. Syst. Lett., 6 (3): 53-56 (2014)