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Другие публикации лиц с тем же именем

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure., , , и . ITC, стр. 1-9. IEEE, (2017)Fault equivalence identification in combinational circuits using implication and evaluation techniques., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 922-936 (2003)Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction., , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1497-1505 (2017)Defect diagnosis based on DFM guidelines., , , и . VTS, стр. 206-211. IEEE Computer Society, (2010)Test Modification for Reduced Volumes of Fail Data., , и . ACM Trans. Design Autom. Electr. Syst., 22 (4): 67:1-67:17 (2017)A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction., , и . ATS, стр. 138-143. IEEE Computer Society, (2016)Innovative practices session 5C: Advancements in test -keeping moore moving!. VTS, стр. 1. IEEE Computer Society, (2015)Using Scan-Dump Values to Improve Functional-Diagnosis Methodology., , , , , и . VTS, стр. 231-238. IEEE Computer Society, (2007)An Experimental Study of N-Detect Scan ATPG Patterns on a Processor., , , , , и . VTS, стр. 23-30. IEEE Computer Society, (2004)Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits., , и . VTS, стр. 181-186. IEEE Computer Society, (2002)