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Bridging RTL and gate: correlating different levels of abstraction for design debugging.

, , , , and . HLDVT, page 73-80. IEEE Computer Society, (2007)

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System Synthesis for Networks of Programmable Blocks, , , and . CoRR, (2007)Verification Approach of Metropolis Design Framework for Embedded Systems., , and . Int. J. Parallel Program., 34 (1): 3-27 (2006)Runtime Deadlock Analysis of SystemC Designs., , , , and . HLDVT, page 187-194. IEEE Computer Society, (2006)Assertion-based power/performance analysis of network processor architectures., , , , , and . HLDVT, page 155-160. IEEE Computer Society, (2004)Efficient methods for embedded system design space exploration., , , and . DAC, page 607-612. ACM, (2000)Simulation Trace Verification for Quantitative Constraints., , , and . Embedded Software for SoC, Kluwer / Springer, (2003)eBlocks - an enabling technology for basic sensor based systems., , , and . IPSN, page 422-427. IEEE, (2005)Memory subsystem simulation in software TLM/T models., , and . ASP-DAC, page 811-816. IEEE, (2009)Metropolis: An Integrated Electronic System Design Environment., , , , , and . Computer, 36 (4): 45-52 (2003)Synchronous approach to the functional equivalence of embeddedsystem implementations., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (8): 1016-1033 (2001)