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An improved algorithmic ADC clocking scheme., , and . ISCAS (1), page 589-592. IEEE, (2004)A Power Efficient SAR Algorithm for High Resolution ADCs., , , , , , and . ISCAS, page 1-5. IEEE, (2018)Power Optimized Comparator Selecting Method For Stochastic ADC., , , , , , and . ISCAS, page 1-4. IEEE, (2018)Digital techniques for improving the accuracy of data converters., , and . IEEE Communications Magazine, 37 (10): 136-143 (1999)A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter., , , and . IEEE J. Solid State Circuits, 43 (2): 414-424 (2008)A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback., , , , , , and . IEEE J. Solid State Circuits, 44 (9): 2392-2401 (2009)Ring Amplifiers for Switched Capacitor Circuits., , , , , and . IEEE J. Solid State Circuits, 47 (12): 2928-2942 (2012)Sensitivity Analysis for Oscillators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1521-1534 (2008)Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC., , , , , , and . IEEE J. Solid State Circuits, 45 (4): 719-730 (2010)A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique., and . IEEE J. Solid State Circuits, 39 (9): 1468-1476 (2004)