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FPGA architecture for noise filters on a reconfigurable processor.

, and . CATA, page 250-253. ISCA, (1999)

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High-performance VLSI architecture for adaptive scaling.. Real-Time Image Processing, volume 6063 of SPIE Proceedings, page 60630C. SPIE, (2006)Hardware/software implementation 3-way algorithm for image encryption., and . Security and Watermarking of Multimedia Contents, volume 3971 of SPIE Proceedings, page 274-285. SPIE, (2000)Design of high-performance coprocessor for color error diffusion.. Color Imaging: Processing, Hardcopy, and Applications, volume 5293 of SPIE Proceedings, page 370-380. SPIE, (2004)Image encryption for secure Internet multimedia applications., and . IEEE Trans. Consumer Electronics, 46 (3): 395-403 (2000)FPGA architecture for noise filters on a reconfigurable processor., and . CATA, page 250-253. ISCA, (1999)A Feature Extraction Application on a Reconfigurable Image Processor., and . IVCNZ, page 352-356. The University of Auckland, (1998)A high performance parallel architecture of H.264 intra prediction for motion estimation.. Real-Time Image Processing, volume 6811 of SPIE Proceedings, page 68110C. SPIE, (2008)Architecture of an application-specific processor for real-time implementation of H.264/AVC sub-pixel interpolation.. J. Real-Time Image Processing, 4 (1): 43-53 (2009)Image encryption for multimedia applications., and . CATA, page 203-206. ISCA, (2000)Reconfigurable Hardware for Encryption., , and . Applied Informatics, page 554-557. IASTED/ACTA Press, (1999)