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Disambiguation of "Chen, Chih-Ang"

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Low power state assignment targeting two-and multi-level logic implementations.

, , , and . ICCAD, page 82-87. IEEE Computer Society / ACM, (1994)

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Yung-chih Chen

Chih-Chun Chen

Chih-Hwa Chen

Chih-Chung Chen

Yen-Chih Chen

 

Other publications of authors with the same name

BIST Test Pattern Generators for Stuck-Open and Delay Testing., and . EDAC-ETC-EUROASIC, page 289-296. IEEE Computer Society, (1994)Low power state assignment targeting two-and multi-level logic implementations., , , and . ICCAD, page 82-87. IEEE Computer Society / ACM, (1994)A Methodology to Design Efficient BIST Test Pattern Generators., and . ITC, page 814-823. IEEE Computer Society, (1995)Design of efficient BIST test pattern generators for delay testing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (12): 1568-1575 (1996)BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms., and . IEEE Trans. Computers, 45 (3): 257-269 (1996)A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts., and . DAC, page 209-214. ACM Press, (1996)Efficient BIST TPG design and test set compaction for delay testing via input reduction., and . ICCD, page 32-39. IEEE Computer Society, (1998)Efficient BIST TPG design and test set compaction via input reduction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (8): 692-705 (1998)