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Disambiguation of "Mahapatra, Anushree"

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Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 384-396 (February 2023)

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Lakshman Mahapatra

Suddhasatta Mahapatra

Subhashree Mahapatra

Usha Deka Mahapatra

 

Other publications of authors with the same name

Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Post-Quantum Signature Schemes., , , and . CoRR, (2022)Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 384-396 (February 2023)Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators., , , , , , and . Microprocess. Microsystems, (2019)Hardware Performance Counters: Ready-Made vs Tailor-Made., , , and . ACM Trans. Embed. Comput. Syst., 20 (5s): 65:1-65:26 (2021)A Golden-Free Approach to Detect Trojans in COTS Multi-PCB Systems., , , , , and . IEEE Micro, 43 (5): 64-76 (September 2023)S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis., and . IEEE Embed. Syst. Lett., 6 (3): 53-56 (2014)Accelerating cycle-accurate system-level simulations through behavioral templates., , and . Integr., (2018)VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration., and . Integr., (2019)Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration., and . ISCAS, page 1-5. IEEE, (2019)