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Disambiguation of "Mitra, Subhasish"

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Optimized self-tuning for circuit aging.

, , , , , , , and . DATE, page 586-591. IEEE Computer Society, (2010)

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Uwe Mitransky

Thomas Mitra

Mitra Westermann

Mitra Pourmansour

Mitra Nikpay

 

Other publications of authors with the same name

System-Level Effects of Soft Errors in Uncore Components., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1497-1510 (2017)Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection., , , , , , , , and . CoRR, (2021)Overcoming Early-Life Failure and Aging for Robust Systems., , , , and . IEEE Des. Test Comput., 26 (6): 28-39 (2009)Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits., , , , , , , and . DAC, page 1-6. IEEE, (2023)A structured approach to post-silicon validation and debug using symbolic quick error detection., , , and . ITC, page 1-10. IEEE, (2015)Packet-Based Input Test Data Compression Techniques., , and . ITC, page 154-163. IEEE Computer Society, (2002)H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing., , , , , , , , and . ITC, page 1229-1238. IEEE Computer Society, (2003)Probabilistic analysis of Gallager B faulty decoder., , , , and . ICC, page 7019-7023. IEEE, (2012)Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs., , , and . DATE, page 1006-1009. IEEE, (2019)TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs., , , , , , , , , and 2 other author(s). DAC, page 74:1-74:10. ACM, (2018)