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Invited - Specification and modeling for systems-on-chip security verification.

, and . DAC, page 66:1-66:6. ACM, (2016)

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Challenges in code generation for embedded processors., , , , , , , and . Code Generation for Embedded Processors, page 48-64. Kluwer, (1994)Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1692-1705 (2018)Power-driven Design of Router Microarchitectures in On-chip Networks., , and . MICRO, page 105-116. IEEE Computer Society, (2003)Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models., , and . ASP-DAC, page 154-159. IEEE, (2022)The Quest for Efficient Boolean Satisfiability Solvers., and . CADE, volume 2392 of Lecture Notes in Computer Science, page 295-313. Springer, (2002)Embedded Software Implementation Tools for Fully Programmable Application Specific Systems.. EMSOFT, volume 2211 of Lecture Notes in Computer Science, page 254-256. Springer, (2001)Zchaff2004: An Efficient SAT Solver., , and . SAT (Selected Papers, volume 3542 of Lecture Notes in Computer Science, page 360-375. Springer, (2004)Solving Quantified Boolean Formulas with Circuit Observability Don't Cares., and . SAT, volume 4121 of Lecture Notes in Computer Science, page 368-381. Springer, (2006)Error-Tolerant Processors: Formal Specification and Verification., , and . ICCAD, page 286-293. IEEE, (2015)Usage-Based RTL Subsetting for Hardware Accelerators., , and . ICCAD, page 73:1-73:9. ACM, (2022)