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Disambiguation of "Namba, Kazuteru"

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Path Delay Fault Test Set for Two-Rail Logic Circuits.

, and . PRDC, page 347-348. IEEE Computer Society, (2008)

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Kazuteru Nonomura

Kazuteru Fukui

Preveen Kumar Nambaru

 

Other publications of authors with the same name

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems., and . IEEE Trans. Computers, 65 (12): 3794-3801 (2016)Parallel Decodable Two-Level Unequal Burst Error Correcting Codes., and . IEEE Trans. Computers, 64 (10): 2902-2911 (2015)Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits., and . IEEE Trans. Computers, 60 (10): 1459-1470 (2011)L band circularly polarized SAR onboard microsatellite., , , , , , , , , and 3 other author(s). IGARSS, page 5382-5385. IEEE, (2017)Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)., and . IEEE Trans. Computers, 68 (2): 301-306 (2019)Extending Non-Volatile Operation to DRAM Cells., , and . IEEE Access, (2013)New 4T-based DRAM cell designs., , and . ACM Great Lakes Symposium on VLSI, page 199-204. ACM, (2014)Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement., , and . IEICE Trans. Inf. Syst., 97-D (3): 533-540 (2014)Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (9): 2295-2303 (2009)Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (6): 1426-1430 (2002)