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MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes.

, , , , , , , , and . ICCAD, page 7. ACM, (2016)

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Towards Memory-Efficient Neural Networks via Multi-Level in situ Generation., , , , , , and . ICCV, page 5209-5218. IEEE, (2021)Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization., , , , , , , , , and 31 other author(s). CoRR, (2020)ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design., , , , , , , , and . DATE, page 1-6. IEEE, (2023)Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond., , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 1:1-1:2 (2014)On stress aware active area sizing, gate sizing, and repeater insertion., and . ISPD, page 35-42. ACM, (2009)ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction., , , and . DAC, page 504-509. ACM, (2008)Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis., , , , and . DAC, page 148-153. IEEE, (2007)AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection., , , and . DAC, page 795-800. ACM, (2011)High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths., , , and . DAC, page 161:1-161:6. ACM, (2015)PASAP: power aware structured ASIC placement., and . ISLPED, page 395-400. ACM, (2010)