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ILP-Based Modulo Scheduling and Binding for Register Minimization.

, , , , , and . FPL, page 265-271. IEEE Computer Society, (2018)

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Automatic high-level synthesis of multi-threaded hardware accelerators., , and . FPL, page 1-4. IEEE, (2014)SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis., , , , , and . FPT, page 36-44. IEEE, (2019)Experiences Building an MLIR-Based SYCL Compiler., , , , , , , and . CGO, page 399-410. IEEE, (2024)Detecting Kernels Suitable for C-Based High-Level Hardware Synthesis., and . UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld, page 1157-1164. IEEE Computer Society, (2016)On Demand Specialization of SYCL Kernels with Specialization Constant Length Allocations (SCLA)., , , , , , and . IWOCL, page 21:1-21:2. ACM, (2024)The Scale4Edge RISC-V Ecosystem., , , , , , , , , and 17 other author(s). DATE, page 808-813. IEEE, (2022)Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling., , , , , and . Euro-Par, volume 11725 of Lecture Notes in Computer Science, page 170-183. Springer, (2019)Extending LLVM for Lightweight SPMD Vectorization: Using SIMD and Vector Instructions Easily from Any Language., , , and . CGO, page 278-279. IEEE, (2019)Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators., , , , , and . ICCD, page 350-357. IEEE Computer Society, (2018)NoFTL-KV: TacklingWrite-Amplification on KV-Stores with Native Storage Management., , , , , and . EDBT, page 457-460. OpenProceedings.org, (2018)