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Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.

, , , , , , , , and . ECCTD, page 1-4. IEEE, (2015)

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Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection., , , , and . ISCAS, page 385-388. IEEE, (2009)ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure., and . ISCAS (2), page 1182-1185. IEEE, (2005)On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process., and . ISCAS (5), page 529-532. IEEE, (2002)Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology., and . ISCAS (2), page 577-580. IEEE, (2004)A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals., and . ISCAS (2), page 573-576. IEEE, (2004)Design considerations and clinical applications of closed-loop neural disorder control SoCs., , , , , , , , and . ASP-DAC, page 295-298. IEEE, (2017)An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process., and . CICC, page 233-236. IEEE, (2008)On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs., , and . CICC, page 361-364. IEEE, (2006)On-glass digital-to-analog converter with gamma correction for panel data driver., , and . ICECS, page 202-205. IEEE, (2008)Design of Multiple-Charge-Pump System for Implantable Biomedical Applications., and . BioCAS, page 1-4. IEEE, (2018)