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Disambiguation of "Higami, Yoshinobu"

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Improvement of the processors operating ratio in task scheduling using the deadline method.

, , and . Enhanced Methods in Computer Security, Biometric and Artificial Intelligence Systems, Springer, (2005)

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Yoshinobu Kumazawa

 

Other publications of authors with the same name

On the fault diagnosis in the presence of unknown fault models using pass/fail information., , , , and . ISCAS (3), page 2987-2990. IEEE, (2005)On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects., , , , and . ISCIT, page 1-5. IEEE, (2017)Formulation of a Test Pattern Measure That Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (12): 1456-1463 (2020)Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits., , , , and . ASP-DAC, page 659-664. IEEE, (2006)Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2842-2850 (2017)Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3506-3513 (2008)Test cost reduction for logic circuits: Reduction of test data volume and test application time., , , and . Syst. Comput. Jpn., 36 (6): 69-83 (2005)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (1996)Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits., , , , and . Asian Test Symposium, page 63-. IEEE Computer Society, (2001)Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set., , , and . Asian Test Symposium, page 216-221. IEEE Computer Society, (2004)